PASSAT 2.0: A multi-functional SAT-based testing framework

Abstract

An important step in the manufacturing process is the postproduction test. Here, a test set is applied to each manufactured chip in order to detect defective devices. The test set is typically generated by ATPG (Automatic Test Pattern Generation) algorithms. Classical ATPG algorithms work on a gate-level netlist and use structural knowledge and heuristics to guide the search in order to obtain a test set. Additionally, the use of ATPG is coupled or accompanied by other test techniques to increase the quality and the compaction of the test set. For example, timing-aware ATPG integrates timing information into the search process to guide the heuristic towards determining the longest paths and n-detection test generation is used to increase the detection quality for unmodeled defects. Fault simulation is applied as a post-processing technique to remove detected faults from the fault list and, by this, to decrease the pattern count as well as the overall ATPG run time. Static and dynamic test compaction techniques are further used for test set compaction. All these techniques are well developed. However, solving them separately limits the quality of the results.