Increased CMOS IC stuck-at fault coverage with reduced I/sub DDQ/ test sets

Abstract

The authors discuss the significant improvements that were achieved when a conventional ATPG (automatic test pattern generation) algorithm was modified to generate test sets suitable for I/sub DDQ/ testing. These improvements include increased SAF (stuck-at-fault) coverage, reduced vector set sizes, coverage of logically redundant SAFs and multiple SAFs, increased coverage of CMOS IC non-SAF defects, and reduced CPU cost for ATPG and fault simulation. This reduction in computational complexity for I/sub DDQ /based ATPG enables test generation for much larger circuits than previously possible. Additionally untestable faults can be further categorized to identify SAFs that are truly 'don't-care faults,' thereby offering a more realistic assessment of actual fault coverage. >