Partitioned register files for VLIWs

Abstract

An ideal VLIW architecture requires a large multiport registerfile that is currently not realizable an practice. We analyze a Limited Connectivity VLIW architecture as a realizable alternative that limits the number of ports. We present a fine-grain code partitioning method for this model. The partitioning scheme was applied to a number of standard benchmarks by varying the number ports on a RF, the number of partitions and the communication bandwidth between partitions. We present these results, along with a preliminary analysis of architectural tradeoffs in the actual implementation of these Limited Connectivity VLIWs.