Partial SOI power LDMOS with a variable low-k dielectric buried layer and a buried p-layer

Abstract

A high voltage LDMOS on partial silicon-on-insulator (PSOI) with a variable low-k (relative permittivity) dielectric buried layer (VLKD) and a buried p-layer (BP) is proposed (VLKD BPSOI). In the vertical direction, the low k value enhances the electric field strength in the buried dielectric (E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</sub> ) and the Si window makes the substrate share the voltage drop, which leads to a high vertical breakdown voltage (BV). In the lateral direction, three interface field peaks are introduced by the BP, Si window and the VLKD, which modulates the fields in the top Si layer, VLKD layer and the substrate. A high BV is therefore obtained. Furthermore, the BP reduces the special on-resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> ) and the Si window alleviates the self-heating effect (SHE). Compared with the conventional PSOI, BV of VLKD BPSOI is enhanced by 43.5% and R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> is decreased by 26.5%.