Partial SOI Power LDMOS With a Variable Low-$k$ Dielectric Buried Layer and a Buried P Layer

Abstract

A power LDMOS on partial silicon on insulator (PSOI) with a variable low-k dielectric (VLKD) buried layer and a buried p (BP) layer is proposed (VLKD BPSOI). At a low k value, the electric field strength in the buried dielectric (Ej) is enhanced, and a Si window makes the substrate share the vertical voltage drop, leading to a high vertical breakdown voltage (BV). Moreover, three interface field peaks are introduced by the BP, the Si window, and the VLKD, which modulate the fields in the SOI layer, the VLKD layer, and the substrate; consequently, a high BV is obtained. Furthermore, the BP reduces the specific ON-resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> ), and the Si window alleviates the self-heating effect (SHE). The BV for VLKD BPSOI is enhanced by 34.5%, and R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> is decreased by 26.6%, compared with those for the conventional PSOI, and VLKD BPSOI also maintains a low SHE.