Abstract

This paper presents a technique to estimate the coefficients of a multiple-look-up table (LUT) digital predistortion (DPD) architecture based on the partial least-squares (PLS) regression method. The proposed 3-D distributed memory LUT architecture is suitable for efficient FPGA implementation and compensates for the distortion arising in concurrent dual-band envelope tracking power amplifiers. On the one hand, a new variant of the orthogonal matching pursuit algorithm is proposed to properly select only the best LUTs of the DPD function in the forward path, and thus reduce the number of required coefficients. On the other hand, the PLS regression method is proposed to address both the regularization problem of the coefficient estimation and, at the same time, reducing the number of coefficients to be estimated in the DPD feedback identification path. Moreover, by exploiting the orthogonality of the PLS transformed matrix, the computational complexity of the parameters’ identification can be significantly simplified. Experimental results will prove how it is possible to reduce the DPD complexity (i.e., the number of coefficients) in both the forward and feedback paths while meeting the targeted linearity levels.

Highlights

  • E NVELOPE tracking (ET) power amplifiers (PAs) have been proposed as an alternative to overcome low power efficiency amplification when using class-AB PAs operated with high back-off levels in order to accommodate the peakto-average power ratio (PAPR) of the transmitted signal

  • In [10], we proposed a modification of the Orthogonal Matching Pursuit (OMP) algorithm, named OMP-look-up table (LUT), that allows searching for the most relevant LUTs of the 3-D distributed memory LUTs (3D-DML) DPD function in the forward path

  • Three different selection methods applied to the original data matrix in the forward path were compared in order to show the model order reduction capabilities while meeting the linearity specifications: a) No OMP: no proper search is carried out, the LUT selection is done by adding consecutive memory terms of both input signals and the slow envelope

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Summary

Introduction

E NVELOPE tracking (ET) power amplifiers (PAs) have been proposed as an alternative to overcome low power efficiency amplification when using class-AB PAs operated with high back-off levels in order to accommodate the peakto-average power ratio (PAPR) of the transmitted signal. The ET architecture requires an envelope modulator capable of efficiently amplifying the signal’s envelope over its whole bandwidth [1] (considered to be, according to the rule of thumb, 3 to 5 times the signal’s bandwidth). Since the overall ET efficiency is calculated as the product of the drain efficiency and the efficiency of the envelope modulator, several efforts have been devoted to design wide bandwidth envelope modulators [2], [3]. Lopez–Bueno is with UPC and Centre Tecnologic de Telecomunicacions de Catalunya (CTTC/CERCA)

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