Abstract
In this paper, we proposed a novel saddle type FinFET (S-FinFET) to effectively solve problems occurring under the capacitor node of a dynamic random-access memory (DRAM) cell and showed how its structure was superior to conventional S-FinFETs in terms of short channel effect (SCE), subthreshold slope (SS), and gate-induced drain leakage (GIDL). The proposed FinFET exhibited four times lower Ioff than modified S-FinFET, called RFinFET, with more improved drain-induced barrier lowering (DIBL) characteristics, while minimizing Ion reduction compared to RFinFET. Our results also confirmed that the proposed device showed improved drain-induced barrier lowering (DIBL) and Ioff characteristics as gate channel length decreased.
Highlights
IntroductionWith decreasing dynamic random-access memory (DRAM) cell size, a recessed channel array transistor (RCAT) has been proposed to overcome the short channel effect (SCE) of conventional
With decreasing dynamic random-access memory (DRAM) cell size, a recessed channel array transistor (RCAT) has been proposed to overcome the short channel effect (SCE) of conventionalMOSFETs with planar channels
We proposed a new device with a partial isolation region under the storage node of conventional S-FinFET
Summary
With decreasing dynamic random-access memory (DRAM) cell size, a recessed channel array transistor (RCAT) has been proposed to overcome the short channel effect (SCE) of conventional. The recessed channel of RCAT has improved short channel effect (SCE), RCAT suffers from low driving current and VTH sensitivity due to the shape of the bottom corner of the recessed channel [1] To solve these problems, a saddle FinFET (S-FinFET). We proposed a new device with a partial isolation region under the storage node of conventional S-FinFET. This structure can be fabricated by using an isotropic dry etching. We thethem optimized parameters of the S-FinFETs buried insulator using a of proposed device andshowed compared with those of conventional of the same size. The simulator is well tuned to predict DRAM cell transistor leakage distribution [10,11]
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