Part I: High-Voltage MOS Device Design for Improved Static and RF Performance

Abstract

In this paper, for the first time, the key design parameters of a shallow trench isolation-based drain-extended MOS transistor are discussed for RF power applications in advanced CMOS technologies. The tradeoff between various dc and RF figures of merit (FoMs) is carefully studied using well-calibrated TCAD simulations. This detailed physical insight is used to optimize the dc and RF behavior, and our work also provides a design window for the improvement of dc as well as RF FoMs, without affecting the breakdown voltage. An improvement of 50% in $R_{\mathrm{{\scriptscriptstyle ON}}}$ and 45% in RF gain is achieved at 1 GHz. Large-signal time-domain analysis is done to explore the output power capability of the device.