Parasitics-aware layout design of a low-power fully integrated complementary metal-oxide semiconductor power amplifier

Abstract

There is a need for efficient fully integrated complementary metal-oxide semiconductor (CMOS) power amplifiers (PAs) for very low power implanted biomedical transceiver systems. However, the parasitics of on-silicon interconnections can cause significant degradation in the performance of radio frequency integrated circuits, in general, and PAs, in particular. In this article, we propose a special layout design approach, which was used to design the layout of a CMOS PA. This approach relies on modeling the interconnection wires in the simulations and optimizing their widths for minimum parasitic effects and hence optimum measured circuit performance. The PA circuit is operating at 2.45GHz and is implemented in a standard 0.18μm CMOS process. Measurement results show that at a supply voltage of 1.4V, the PA delivers an output power of 4.5mW with 28.5% power-added efficiency and a power gain of 21.5dB. Owing to the careful layout design and interconnection optimization, the implemented PA circuit shows good efficiency and demonstrates a good match between the measured and simulated performance characteristics.