Parasitic source and drain resistance in high-electron-mobility transistors

Abstract

The parasitic source and drain resistances of a high-electron-mobility transistor were analyzed in terms of a two layer transmission line model. The analysis showed that a highly conductive cap layer can function as an extension of the alloyed contact provided that tunneling between the cap layer and the channel is significant. The tunneling between the cap layer and the channel was analyzed in terms of a thermionic-field emission model in which a one dimensional time-dependent WKB transmission probability for the barrier was considered as well as Maxwell-Boltzman statistics for the tunneling carrier distribution. The GaAs cap, GaAlAs layer and 2-DEG channel can then be treated as a distributed resistance element with a characteristic coupling length. A reduction of the parasitic resistance can be obtained for a device structure with a short characteristic coupling length even if there exists an ideal alloyed contact to the 2-DEG channel. A multilayer cap consisting of an undoped GaAs layer inserted between the n-type GaAs and n-type GaAlAs is also proposed to reduce the barrier height for tunneling between the cap layer and the channel. The multilayer cap structure is predicted to appreciably reduce the parasitic resistance at room temperature and still be effective at 77 K.