Parasitic inductance extraction and verification for 3D Planar Bond All Module

Abstract

In this paper, the parasitic inductance extraction method is studied in detail. It is analyzed that the value of the lumped power loop inductance will be varying at different switching transients. With the aid of Ansys Q3D Extractor, different values of lumped power loop parasitic inductance are obtained at different time intervals during turn-off process for both upper and lower devices. A dedicated 3D Planar Bond All Module with access to both kelvin and terminal drain-to-source voltage is built, and the parasitic inductance of the module is experimentally extracted by comparing those two voltages in double pulse tests. The experiment result shows good agreement with the simulated parasitic inductance value thus validating the extraction and simulation method.