Effects of parasitic inductance on performance of 600-V GaN devices

Abstract

This paper presents a comparison of two identical gallium nitride (GaN) cascode transistors with different TO-220 packaging configurations. The transistors were analyzed using a precision frequency domain impedance analyzer; and lumped, per-terminal estimates were developed for the parasitic package inductance of each device. It was found that the devices have different per-terminal lead inductances, despite the fact that the dies are manufactured using similar processes. To assess the impact of the different package configurations, the devices were subjected to double pulse tests (DPT), and switching loss measurements were taken. The devices were also modeled using SaberRD (Synopsys) and simulated in the same DPT experimentally implemented. The results show good agreement between the models' predicted behavior and measured behavior. These validated models can be used to further predict the impact of each parasitic inductance on the device's transient performance. This is particularly essential for GaN-based power electronics, where the parasitic inductance can significantly affect device performance and reliability.