Parasitic Inductance and Capacitance-Assisted Active Gate Driving Technique to Minimize Switching Loss of SiC MOSFET

Abstract

High di/dt and dv/dt of SiC MOSFET cause a considerable amount of overshoot in device voltage and current during switching transients in the presence of inverter layout parasitic inductance and load parasitic capacitance. The excessive overshoots in device voltage and current cause failure of the device. Moreover, these uncontrolled overshoots increase the switching loss in the inverter. It is difficult to reduce parasitic inductance beyond a certain point. This paper proposes an active gate driving technique, which allows inverter to operate with moderate amount of layout parasitic inductance and load parasitic capacitance. The proposed technique dramatically reduces switching loss of the SiC MOSFET with the help of existing parasitic elements. The proposed switching loss reduction technique is termed as quasi zero switching . The developed active gate driver has been tested in a double pulse test setup and a 10 kW two-level voltage source inverter driving an induction motor.