Abstract
This paper proposes a novel digital active gate drive method, aiming to optimize high-power IGBT’s switching losses and stresses. Compared to common voltage-source gate driver, the proposed method can reduce switching losses while being able to suppress IGBT current and voltage overshoots during switching transients. The proposed method is described in detail and is experimentally verified under various operating points. Additionally, since parasitic inductances in the commutation and gate loop are critical to gate driver’s stability analysis and online calculations of collector current and current slope, an extraction principle is proposed and verified by experiments.
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