Abstract
The impact of parasitic capacitance in micron and submicron CMOS/SOS implementations is explored. Relative measures of parasitic fringing and interconnect capacitance associated with ring oscillator and high-speed 1/64 frequency divider (400 MHz at 4V) circuit layouts are investigated. Parasitic capacitance figures of merit are analyzed in terms of several key geometrical dimensions, from which sensitivity of parasitic influence on circuit speed to departure from ideal scaling laws can be deduced. Analytical and numerical results and design considerations moderating deleterious effects of parasitic capacitance in down scaling from 2 to 1 to 0.5µm CMOS/SOS technologies are discussed.
Published Version
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