Parallel MPSoC Simulation and Architecture Evaluation

Abstract

In order to exploit the parallelism of a multi-core host machines, this chapter introduces four novel parallel discrete-event simulation techniques, which exploit the parallelism of the simulated target architectures and applications for parallel simulation on the host machine. In order to guarantee timing results equal to sequential simulation, a correct synchronization and activation of the parallel host threads are required, which is differently realized for each of the four proposed parallelization techniques. Furthermore, parallel simulation allows evaluating different architectural design choices such as the number of tiles, internal tile structure, and selection of cores within each tile. Here, case studies regarding performance and costs trade-offs of different heterogeneous invasive architecture variants are presented. The combination of the provided simulation techniques provides a holistic simulation approach for modern multi- and many-core architectures that is fast and accurate enough in timing to simulate parallel invasive applications so to gain valuable insight into their dynamic behavior and to evaluate different architecture alternatives. The reader will understand the presented concepts for modeling and accelerating the simulation of different hardware components on architecture level and how to combine them to a unified full-system simulation.