Abstract
Parallel architectures are often described based on the number of instruction and data streams, namely single and multiple data and instruction streams. A complete taxonomy of different combinations of instruction streams and data was given in [Flynn, 1972]. To evaluate the performance delivered by these architectures on a given computation, speedup is defined as \(\frac{{{{T}_{s}}}}{{{{T}_{p}}}}\), where T s is the time taken by the best sequential algorithm, and T p is the time taken by the parallel algorithm under consideration. The higher the speedup, the better the performance The motivation for measuring speedup is that it indicates whether or not an algorithm scales. An algorithm that has near linear speedup on sixteen processors may not exhibit similar speedup on hundreds of processors. However, an algorithm that delivers very little or no speedup on only two processors will certainly not scale to large numbers of processors.
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