Abstract
The importance of circuit simulation in the design of VLSI circuits has channelised research work in the direction of finding methods to speedup this highly compute-intensive problem. On one hand, attempts have been made to find better algorithms and use faster hardware; and on the other hand, to use parallel architectures for accelerating the circuit simulation task. In this paper, we examine the various issues involved in parallelizing two well-known circuit simulation approaches – direct methods and relaxation methods. A number of parallel computer architectures which have been used for this purpose are also surveyed.
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