SEMU: a parallel processing system for timing simulation of digital CMOS VLSI circuits

Abstract

Describes a hardware accelerated approach to MOS VLSI timing simulation. Accurate timing simulations are crucial to the design and verification of MOS VLSI circuits, but can take prohibitively large amounts of time on an engineering workstation. The SEMU system consists of a 4/spl times/4 array of full custom floating point processors on a single SUN/VME board, runtime library, and the EMU timing simulation software. The basic building block of this parallel architecture is a processor called Smoke that contains a fully integrated 32-bit floating point/integer unit, four parallel ports for inter-processor communication, a parallel port for global communication, and a small but powerful instruction set. Performance of a 20 MHz system on a 4/spl times/4 Smoke processor array is 25-30 times faster than EMU on a 40 MHz Sparc2 Workstation. >