Parallel function invocation in a dynamic argument-fetching dataflow architecture

Abstract

The basic structure of a dynamic data-flow architecture based on the argument-fetching data-flow principle is outlined. In particular, the authors present a scheme to exploit fine-grain parallelism in function invocation based on the argument-fetching principle. They extend the static architecture by associating a frame of consecutive memory space for each parallel function invocation, called a function overlay, and identify each invocation instance with the base address of its overlay. The scheme gains efficiency by making effective use of the power provided by the argument-fetching data-flow principle: the separation of the instruction scheduling mechanism and the instruction execution. To handle function applications and memory management, the proposed architecture will have a memory overlay manager that is separate from the pipelined execution unit. To verify the design, a set of standard benchmark programs was mapped onto the new architecture and executed on an experimental general-purpose data-flow architecture simulation testbed. >