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https://doi.org/10.1109/cicc.1988.20812
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Cite Publication Date: May 16, 1988 |
 Citations: 14 |
Affiliation: Stanford University, Intel (United States)
A parallel circuit simulator was implemented on the iPSC system. Concurrent model evaluation, hierarchical BBDF (bordered block diagonal form) reordering, and distributed multifrontal decomposition to solve the sparse matrix are used. A speedup of six times has been achieved on an eight-processor iPSC hypercube system. >
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