Parallel Discrete Event Simulation: Opportunities and Pitfalls

Abstract

Discrete event models are used in a wide variety of applications, ranging from flexible manufacturing systems to digital electronics. A common feature to all these domains is the complexity of the systems under investigation. In general, detailed models of real size designs are analytically intractable and numerically prohibitive to evaluate. Discrete event simulation is one possibility to gain insight in the behaviour and performance characteristics of complex systems. However, the lack of efficient simulation tools makes discrete event simulation of large systems excessively slow on conventional computers. This fundamental problem can be addressed according to two different strategies: an adaptation of the simulation model and the utilization of more powerful computers. In this paper, an overview of various approaches of the second class to upspeed discrete event simulation is given. It is shown that the traditional sequential simulation algorithm cannot be parallellized, in order to take advantage of opportunities offered by parallel computer architectures. It will be indicated that in order to obtain a performance gain in terms of the only realistic benchmark possible, a sequential simulation on a single processor, careful tuning is required in order to match software requirements with hardware resources. The most important parameters of this problem will be highlighted.