PAM-4 receiver with integrated linear TIA and 2-bit ADC in 0.13 μm SiGe:C BiCMOS for high-speed optical communications

Abstract

This paper presents the design and electrical characterization of an optical receiver and demodulator for PAM-4 encoded data signals. The prototype, fabricated in a 0.13 μm SiGe:C BiCMOS technology, comprises a linear TIA input stage followed by a 2-bit flash ADC, and is designed to support up to 100 Gb/s data rate while dissipating 650 mW of average power. The TIA stage was independently characterized, featuring 54 dB-Ω differential transimpedance, 3-dB bandwidth of 60 GHz and less than 12 pA/VWz average input referred current noise density. The complete module was measured to receive up to 24 GBd (setup-limited) PAM-4 PRBS7 data signals at a BER of 4 · 10−12 and 1·10−13 for the LSB and MSB, respectively, with input amplitude as low as 580 μA pp . Clear NRZ eye diagrams up to 50 Gb/s are also reported, which demonstrate the high-speed operation capability. The integration of both TIA and dedicated ADC in the same chip allows for a custom design, optimized in terms of power dissipation and footprint, for the next generation optical transceivers.