Abstract
A 6-bit low-power compact flash ADC has been designed. MOS current-mode threshold logic gates are employed to obtain a compact encoder circuit block. This reduces the number of transistors in the encoder to one sixth that required in a conventional scheme. A dynamic comparator is also adopted to decrease the power consumption. Circuit simulation assuming a standard 0.35-/spl mu/m CMOS technology reveals that the present 6-bit ADC operates at 500 MHz with a power consumption as low as 113 mW. The figure of merit, which is defined as the power divided by the product of 2/sup bit/ and the sampling frequency, is improved by a factor of two compared with conventional approaches.
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