Design of 6-Bit Two-step Flash ADC for High Speed and Low Power Applications

Abstract

In this paper, 6-bit two-step Flash ADC operated at the 2 GS/s is designed, with optimized performance for frequency domain applications. To get the best performance, the coarse convertor of 2-bit and the fine convertor of 4-bit are chosen. The comparator design is done with optimum power and area with two power supplies. Intermediate state accuracy increased by thermometer coded current steering DAC. The DNL and INL specifications are chosen to be 0.8 LSB and 0.9 LSB respectively. For a sampling frequency of 2 GS/s, the SFDR is greater than 47 dbc for the signal from dc to 70 MHz and the SNR is greater than 34 dB. The power consumption is only 9.35 mW, and figure of merit equals to 0.146 (pJ/step) at the power supplies of 1.8 V and 0.75 V. The key building blocks like sample and hold circuit, comparator, residue amplifier, current steering DAC are designed. Layout and simulation of functional element at the block level is performed. All the designs are done in 180 nm CMOS technology from UMC Cadence EDA tool suite. Keywords: Two-step Flash ADC, sample and hold circuit, comparator, residue amplifier, current steering DAC