Page associative caches on Futurebus

Abstract

A cache scheme which uses page associative cache descriptors can offer advantages in terms of its impact on cache coherence in the presence of paged transactions, and on the use of local memory to minimize bus loading. It can also be used to preserve cache coherence when processor accesses are cached, i.e. a logical cache, in the presence of an external memory management unit. This paper proposes a mechanism for page associative cache operation for use with Futurebus systems, and analyses how such a cache would overcome the problems common to cache memory designs. Cache protocols are not included in the current Futurebus specification IEEE 896.1, recently standardized, but will be added after further development. Performance of page associative caches is compared with directly mapped caches and fully associative caches.