Abstract
Recent developments in computer-aided design (CAD) have made highly automated layout of custom emitter coupled logic (ECL) circuits possible. These layouts have a much higher circuit and power density than gate array designs. It is now possible to place an entire ECL microprocessor, including floating point unit and cache memory, on one large die. To demonstrate the capability of supporting such a die, low-cost air-cooled single-chip packaging was built and tested for a 12.6-mm by 15.4-mm die. The plastic pin grid array (PPGA) package supplied the required current and maintained junction temperatures at less than 100 degrees C while dissipating 150 W. This required innovation in five areas: die metalization, bondwire layout, PPGA package design, die attach, and cooling by a thermosiphon.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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