Package Chip Defect Reduction on Integrated Circuit

Abstract

This research applies Six Sigma approach in order to reduce defect by increasing the assembly process capability index (Cpk) of Integrated Circuit (IC) production process. This study applies five phases (DMAIC) of Six Sigma approach beginning with define (D), measure (M), analyze (A), improve (I) and control (C) phases, respectively. The response of the research identified in the define phase is the chipped width with Cpk of 0.66 determined from the measure phase. The half-factorial experiments are implemented in the analyze phase to find the significant factors which are water temperature, water pressure and feed rate. In improve phase, the additioanl expriments are performed according to the Box-Behnken design in order to determine the non-linear relation between the chipped width and all mentioned factors. The optimal setting of each factors are determined by applied the response surface optimizer. Under the optimal setting, the control charts are used in the control phase to monitor the chipped width. The resulted Cpk of the response is increased to 1.39 which is greater than the one-sided accpetable process capability of 1.25.