Abstract
Path delay faults are tested via selected critical paths in a tested digital circuit. The critical paths can be specified e.g. by static timing analysis (STA), dynamic timing analysis (DTA) and others. Many parameters such as multiple input switching, power supply noise, type of propagated signal edge (rising, falling) and others affecting the signal delay propagation and thus they can increase path criticality. The impact of each parameter to the path delay faults has been solved and published in some papers but their joint effects should be also investigated. A new general technique for path criticality calculation based on influence of multiple parameters, STA and new defined formula for path criticality calculation has been proposed. A new automatic system, named PaCGen, for critical paths selection is presented in the paper.
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