P‐8: Investigating the Degradation Behaviors for Bottom/Top Gate Sweep under Negative Bias Illumination Stress in Dual Gate InGaZnO Thin Film Transistors

Abstract

This paper investigates illuminated negative bottom/top gate bias effect‐induced degradation behavior in the bottom/top gate sweep for dual gate a‐InGaZnO thin film transistors. The oncurrent conduction behavior in the top gate sweep was attributed to diffusion current, which is dominated by the source side barrier. It was also found that the degradation behaviors are completely different in the bottom and top gate sweep, regardless of bottom gate or top gate stress. When negative bias is applied on the bottom gate under illumination, the degradation behaviors are dominated by hole‐trapping in the gate insulator. However, the degradation behaviors are dominated by holetrapping in the etch‐stop layer when NBIS is operated on the top gate terminal. The different locations of these hole‐trapping regions cause the respective degradation behavior in the bottom/top gate sweep.