P‐6: A Novel Self‐Aligned Lightly‐Doped‐Drain Polysilicon Thin‐Film Transistor Using a Partial Exposure Technique

Abstract

AbstractIn this paper, a novel self‐aligned lightly‐doped‐drain (LDD) Poly‐Si TFT using a partial exposure technique is proposed and demonstrated. The LDD region is self‐aligned to the channel and with a length ranging from 0.4 μm to a few μm. The different LDD lengths can be obtained simply by different layout designs. The partial exposure technique for obtaining the LDD is simple and effective, and does not require any additional mask. Experimental results show that the on/off current ratio of the LDD Poly‐Si TFT with 0.5 μm LDD length and 5 μm channel length is approximately 12 times larger than that of the conventional non‐LDD TFT.