Abstract
In this work, a multi‐phase charge pump topology is proposed to drive the display driver integrated circuits. To achieve high integration and power efficiency simultaneously, a converter with full‐coverage voltage conversion ratios ranging from 1 to 2n is realized while the count of off‐chip capacitors is halved. At the same time, the charging period for each clock phase is designed to be equal and it allows a higher operation frequency of 2n/(n+1) times while the capacitor can still be fully charged. Based on 0.25 µm process, a three‐stage topology has been performed. It has improved the current drivability by 40%–150%. This design is quite suitable for display panels with higher resolution requirements.
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