Abstract
Along with the development of advanced display technology, the specification of display panel gets increasingly demanding, taking more factors into consideration in FPD designs. Because of parasitic resistance and capacitance, marked IR‐Drop effects are detected in high resolution display panel, leading to electrical and optical specification defects therein [1,2]. Power/thermal of the power source line serves as a key index affecting complex FPD designs. In this article, we provide a highly efficient full panel electric‐thermal simulation flow, which facilitates designers to accurately assess the effect of IRDrop and then simulate the power/thermal distribution map of a full panel. Precise simulation of device/wire current and voltage as well as current density also helps to optimize active matrix OLED pixel design.
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