Abstract
This paper presents a robust OxRAM-based nonvolatile flip-flop (NVFF) solution, designed for deep nano-scaled CMOS technologies. Forming, set and reset operations rely on a reliable design approach using thin gate oxide CMOS. The NVFF is benchmarked against a standard FF in 28nm CMOS FDSOI. Non-volatility is added with minimal impact on the FF performances.
Highlights
The new growing area in semiconductor industry is the Internet of Things, which leads to an increased interest in design of Ultra-Low Power (ULP) embedded systems
Several Non-Volatile Flip-Flop (NVFF) solutions realized by adding NV devices to the standard master-slave flip-flop (MSFF) are reported [4,5,6]
Static consumption which is a weak point of advanced CMOS nodes can be (1) minimized in active mode by using thin-film technologies (FDSOI, FinFET) and (2) completely canceled in the sleep mode due to Non-Volatile Memories (NVM)
Summary
The new growing area in semiconductor industry is the Internet of Things, which leads to an increased interest in design of Ultra-Low Power (ULP) embedded systems. Static consumption which is a weak point of advanced CMOS nodes can be (1) minimized in active mode by using thin-film technologies (FDSOI, FinFET) and (2) completely canceled in the sleep mode due to NVM In this case the required ReRAM programming voltages may be above the maximum voltage that ensures reliable transistor operation. VRESET will be above the CMOS operating range if fast switching behavior is targeted (e.g. 1.7V for 10ns reset of 1TG1R structure with wn=400nm) This is true for forming operation, as it typically requires increased voltages (Fig. 1), even without taking the operation speed into consideration. In order to accomplish specified operation modes functions (1) - (4) are realized in logic blocks
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