Abstract
In conventional chip design digital simulation and analog simulation are carried out separately by digital designers and analog designers. Digital designers run block simulation on RTL code and SDF back-annotation post layout simulation which includes the timing information in digital simulator such as ModelSIM. Analog designers simulate the circuit in transistor level analog simulator. Several interface problems are missed in designs because of kick in a true verification between analog and digital blocks till the silicon comes out of the fab. The new digital full-chip design/verification flow combines both digital and analog simulation in a single environment. It provides a critical bridge which links analog and digital blocks and performs the true full chip design and verification. Using this new flow digital designers and analog designers can work closely together and check the full-chip function and interface between digital blocks and analog blocks. Analog behavioral models can be introduced to replace transistor level block which can save simulation time by hundreds of hours on the initial design cycle for functional design. Fast-spice simulator which also has been integrated into mixed-signal flow can be used in the final full chip simulation in which the transistor level simulation is required.
Published Version
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