Abstract
This talk is dedicated to the special session in honor of Prof. Babu Shrink of critical dimensions and stringent technology specifications are posing several planarization challenges in technology development (TD) and high-volume manufacturing (HVM) phases of current and advanced technology nodes. In this talk, we will focus on process challenges related to achieving (a) minimum defects (b) high planarization efficiency with less than 1nm dishing (c) tighter WIW and WID uniformities (d) ultra-smooth post-CMP surface roughness in the order of sub-nanometer. In addition, identifying appropriate endpoint control techniques combined with advanced process control strategies to provide good process margin will also be discussed. Addressing the above challenges in a cost-effective manner is vital for HVM. Root cause analysis and probable working models will be discussed for high-risk process challenges. Based on our understanding, a jist shall be provided about challenges associated with future technology nodes in logic and memory industries, with focus on how (a) technical understanding, (b) change in CMP ecosystem, and (c) AI can help solving technology development and high-volume manufacturing problems.
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