Overlay measurement using the low voltage scanning electron microscope

Abstract

Accurate and precise overlay metrology is essential for the successful fabrication of integrated circuits with sub-micron critical dimensions. We have investigated the use of the low voltage scanning electron microscope (SEM) to measure overlay at the device level and to calibrate the measurements made with optics-based systems. A study of the fundamental aspects of SEM overlay metrology was made on resist/etched silicon as well as resist/silicon test wafers. It was found to be critical to optimize the SEM accelerating voltage, scanning technique, mark design, detector design, and measurement algorithm. 3σ measurement precisions better than 0.010 μm were easily obtained on a variety of samples. SEM tool-induced shift 1 (TIS), when present, was found to be of the same order as the 3σ precision and was negligible in the absence of charging. Finally, a comparison of automated optically-based measurements to SEM overlay measurements was made on advanced integrated circuit production wafers. Agreement was quite good with the average difference less than 0.01 μm and 3σ variation of the difference better than 0.04 μm for marks in resist.