Abstract
A new hardware approach for implementing overcurrent relays is presented in this paper. An overcurrent relay is implemented on a field programmable gate array (FPGA) chip (Xilinx's XC3020-50-PC84C). The hardware design of the overcurrent relay is based on a three-stage pipelined architecture. A relationship that describes the time-current characteristics of the relay in terms of the clock frequency of the chip is developed.
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