Output Impedance Mismatch Effects on the Linearity Performance of Digitally Predistorted Power Amplifiers

Abstract

This paper analyzes the effects of load impedance mismatch in power amplifiers which linearity has been enhanced using various digital predistortion (DPD) algorithms. Two different power amplifier architectures are considered: a class AB and a Doherty amplifier and three model structures for the DPD model are compared: memoryless polynomial (MLP), general memory polynomial (GMP) and Kautz-Volterra functions (KV). This paper provides a sensitivity analysis of the linearized amplifiers under load mismatch conditions and reports the performance when dynamic parameter identification for the DPD is used to compensate for the changes in the load impedance. In general, power amplifiers linearity is sensitive to load impedance mismatch. Linearity may degrade as much as 10 dB (in normalized mean square error) according to the magnitude and the phase of the reflection coefficient provided by the load impedance. However, depending on the amplifier design, the sensitivity to load impedance mismatch varies. While the Doherty amplifier studied show significant linearity degradations in the in-band and out-of-band distortions, the out-of-band distortions of the studied class AB were less sensitive to the load impedance mismatch. In adaptive DPD schemes, the performance obtained in the MLP model does not benefit from the updating scheme and the performance achieved is similar to a static case, where no updates are made. This stresses the memory requirements in the predistorter. When employing the GMP and the KV models in an adaptive DPD scheme, they tackle to a larger extent the linearity degradations due to load impedance mismatch.