Abstract

Power Amplifier (PA) linearization by Digital Pre-Distortion (DPD) using baseband signals is one of the most popular methods for improving wireless transmission systems' efficiency. This research addresses this problem by focusing on reducing the DPD complexity without compromising the linearization system's efficiency. This contribution consists of a DPD structure with memory effects based on the Feed-backed Wiener (FW) system, which results in a pruned Volterra series. A FIR filter is used as a feedback path to compensate for the PA memory effects. The proposed structure is used to linearize an LDMOS PA (50 W - 500 MHz to 2.5 GHz) in the case of LTE/4G signals with different bandwidths and output powers. A comparison in terms of DPD identification and PA linearization performances between the proposed model and the Generalized Memory Polynomial (GMP) model shows that the proposed model presents similar performances, with the advantage of reduced complexity.

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