Optimum design of the execution stage of embedded processors

Abstract

We describe the optimum design of a power conscious highly performable execution stage. It is the core of embedded processors that treat flexible embedded applications like voice recognition, 3D graphics, and image/vision processing, etc. Considering algorithms based on these basic applications, the design principle of the embedded processor's execution stage is reliability, precision, power, speed, and throughput. However, the mixed arithmetic sequence of integer and FP (floating point) numbers frequently used in these algorithms makes it hard to clear the design principle. With respect to this view point, existing microprocessor technology based on scaling and gating techniques have both merits and demerits. Actually, HW/SW (hardware/software) co-design is crucial for not only embedded processors but also the execution stage itself. The execution stage studied in this paper is a wave-pipelined MFU (multifunctional unit) that is the combination of multifunctionalization and wave-pipelining of FUs (functional units). The waved MFU agrees well with overall trade-off design. However, it lacks the fixed design procedure. The standard CAD environment cannot be available because it is dedicated to regular pipelines. Thus, this paper presents the HS/SW co-design approach for the waved MFU. The usefulness is shown by the experimental result.