Fused floating-point add and subtract unit

Abstract

The paper describes the fused floating-point Add-Subtract Unit using IEEE-754 standard 32 bit floating point number representation. In fused add-subtract unit, both add unit and subtract unit perform parallel operation and this approach of fused unit reduces the hardware required and also the cost of designed unit. Besides addition and subtraction if one more operation suppose multiplication is to be performed then a multifunctional design is required. The multi-functional floating-point unit includes a multiplier unit above a Fused Add-Subtract Unit which uses hardware more efficiently in comparison to the separate unit blocks for each operation. This method reduces the area of the designed block but the speed of operation is also reduced. The blocks are reduced based on the common operation between each designed unit. For example, in every unit rounding operation is done after each operation for floating point number. If a common block for rounding is designed then the hardware is reduced. The paper also compares one add unit with fused floating point add-subtract unit and one multifunctional unit