Optimizing Device Dimensions for Dual Material Junctionless Tree-FET: A Path to Improved Analog/RF Performance

Abstract

This comprehensive study delves into the intricate analysis of the electrical and analog/RF performance of the Dual Material (DM) junctionless (JL) Tree-FET. During the optimization process, various DC and analog/RF metrics were taken into account. It is observed that, as the gate length decreases (12 nm to 8 nm), there is an increment in drain induced barrier lowering (DIBL), switching ratio (Ion/Ioff), and subthreshold swing (SS). Conversely, reducing the size of TNS (and WNS) from 10 nm to 5 nm (and 20 nm to 10 nm, respectively) lead to notable improvements, with a 34.4% (21.01%) decrease in SS, 93.19% (58.86%) decrease in DIBL, and 98.6% (41.06%) increase in Ion/Ioff. Furthermore, the analog/RF performance metrics of the device is carefully examined across dimensional variations, revealing significant improvements at the optimal values. Additionally, the study extends to the evaluation of inverter circuit characteristics with DM JL Tree-FET. Remarkably, the static noise margin (SNM) and delay exhibit 337.3 mV and 3.053 ps, respectively, positioning the device as a prime candidate for applications demanding low power consumption and high-frequency operation in future technology nodes.