Optimizing a 3D image reconstruction algorithm: investigating the interaction between the high-level implementation, the compiler and the architecture

Abstract

Digital signal processing and multimedia workloads will be a dominant workload for computer based systems in the near future. In this paper, we evaluate the performance of an important media application, namely a relatively new 3D image reconstruction algorithm, on two platforms: a DSP processor (Texas Instruments TMS320C6701) and a high-performance general-purpose microprocessor (Alpha 21164). Prior to evaluating the performance of both architectural paradigms---very long instruction word (VLIW) versus an in-order superscalar organization---we optimized the algorithm by applying algorithmic optimizations as well as implementation-dependent optimizations. For the VLIW architecture, we obtained a 12X speedup for a 465x320 image; on the Alpha 21164, a 4X speedup was obtained. Thanks to this high speedup, this 3D image reconstruction algorithm becomes useful for real-time use. Next to evaluating the various optimizations, we also discuss the implications of these optimizations on the performance of various architectural structures, such as the branch predictor and the memory hierarchy.