Design methodology of a hardware-efficiency VLIW architecture with highly adaptable data path

Abstract

A digital signal processor (DSP) based on the very long instruction word (VLIW) structure has high computation performance and flexibility, which can be applied in the multi-standard video codecs. With the progress of the fabrication, the VLIW architecture can allocate many computational units to execute many operations in parallel. Every computational unit in the VLIW architecture employing multiple modes can be adjusted to perform different operations. It is difficult to realize these operations in an integrated and low-complexity hardware component. When the computational unit performs an operation, some hardware components in the computational unit would be idle, so as to waste the hardware. Moreover, as the number of computational units is increased, the number of hardware components in idle states is also raised. Hence, in this work, we propose a methodology to design an adaptive mechanism embedded in a VLIW DSP. By performing adaptive operations, the proposed VLIW DSP can utilize hardware components of computational units in maximum to improve the computational performance. In addition, apart from allocating few wires and switching circuits, the proposed adaptive DSP doesn't need to increase hardware components of the architecture and data bandwidth of the register file, so a hardware-efficiency DSP can be achieved. In comparing to the conventional DSPs, the proposed architecture demonstrates the best ratio of computation power over hardware cost to realize the functions of video codecs.