Optimized reactive ion etch process for high performance SiC bipolar junction transistors

Abstract

SiC high power rf devices are slated to replace Si devices to enhance system performance and to reduce overall cost. A common SiC rf bipolar junction transistor (BJT) fabrication process includes homoepitaxial growth of differently doped layers followed by several dry etching steps. In this article the authors will focus on two critical etch processes evaluated on 2in. SiC wafers. The first process is a deep (>5μm) etch for electrical isolation between devices. The second process is a shallow (<0.3μm) precise etch down to the base layer. They present details on a novel etch process for SiC rf BJT fabrication process based on the combination of reactive ion etch (RIE), sheet conductance measurements, and oxidation. The RIE parameters were optimized resulting in smooth etched surfaces and sufficient etch depth uniformity of <8% for shallow etch and <2% for deep etch across 2in. SiC wafers. Their etching process provides a precision (±10nm) emitter etch to the emitter-base junction, even when the actual epit...