Abstract
Multiplication is the commonly used operations in a Central Processing Unit (CPU). The performance of the CPU depends on multiplier which may be slower and may consume significant amount of power. This work presents a low power and high speed multiplier architecture using Vedic mathematics technique. The work also proves the efficiency of Urdhava Tiryakbhyam sutra of Vedic mathematics which shows a difference between actual process of multiplication and Vedic multiplication. Carry Save Adder (CSA) is used in the architecture to have reduced delay. The proposed multiplier circuit is synthesized using Xilinx 13.1 version tool for Field Programmable Gate Array (FPGA) flow and Cadence 12.10 version tool for Application Specific Integrated Circuit (ASIC) flow for the analysis of dynamic power consumption and propagation delay and the design is simulated using Modelsim 6.5 version tool for functional verification.
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