Abstract
A simple model for the propagation delay of source coupled logic gates composed of a differential pair and a common drain output buffer in III-V HEMT technology is proposed. The propagation delay model has been used to develop a design strategy that permits pencil-and-paper design of the gates, accounting for power-delay trade-off. The methodology has been applied to a charge-control high-frequency model of the HEMT, but is general-purpose and applicable also to different models. In the present case, percentage errors lower than 15 % have been found in propagation delay evaluation.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
