Constant power consumption design of novel differential logic gate for immunity against differential power analysis

Abstract

Differential power analysis (DPA) method is frequently used for the non-invasive side-channel attack to hack into the system. This study proposes a novel DPA immune design of basic gates, which show the dense distribution of autocorrelation and strong salience strength around 60%. The design has a highly regular structure with exactly similar evaluation path for both differential outputs, AND-NAND, and OR-NOR which can be easily extended for n -bit inputs. The design effort is minimal as the structure is such that AND-NAND design can be used to obtain OR-NOR function by just changing the placement of inputs. These gates have 0.46× less propagation delay, and 3.7× higher power consumption in comparison to other published work. The designs are simulated using Cadence tool with TowerJazz CMOS 180 nm technology with a power supply of 1.8 V.