Optimized counting threshold Built-in redundancy analysis for memories

Abstract

Memory plays pivotal roles in any System on chip (SOC) design. While manufacturing the memories, there may be a chance of defects in the memory so it will influence its total yield. So, it is necessary to ensure the defect less memory while manufacturing itself. There are certain techniques like the Built-in self-test (BIST) to test the working condition of the memory in the chip itself. If the memory is repairable then it will not affect the total yield. There are repairing mechanisms such as Built-in redundancy analysis (BIRA), which can be used to repair the memory in the chip itself. In this paper, we propose anoptimized Built-In Redundancy analysis algorithm, which uses Customized Fibonacci Based Test Pattern Generation (CFBTPG) and optimized counting threshold logic for testing and repairing analysis.The proposed method shows better results in comparing with the existing counting threshold algorithm and commonly used Comprehensive Real-time Exhaustive Search Test and Analysis (CRESTA) algorithms.